In present ULSI (ultra-large-scaled-integration) structures, high circuit speed, high packing density and low power dissipation are essential. As a result, feature sizes must be scaled downward, and the interconnect related time delays become the major limitation. Elemental aluminum and its alloys have been the traditional metals used to form lines and plugs in IC's; however, aluminum has a relatively high resistivity and its electromigration susceptibility can lead to the formation of voids in the metal lines. Therefore copper has been considered as a replacement material to aluminum in interconnect metallurgy system due to its lower resistivity and higher reliability. Replacing current aluminum interconnect materials by copper has become a critical goal for semiconductor manufacturers especially for sub-quarter micron devices.
However, there are serious problems related to process integration of copper to integrated circuits. It is difficult to pattern and remove copper by dry etching, because its reaction product is not gaseous. The conventional approach of depositing a film and then patterning it cannot be relied upon for producing copper interconnections on substrates. Another problem lies in copper's extremely high diffusivity in silicon dioxide, and minute amount of diffused copper atoms in the transistors' active regions will play havoc with their device characteristic.
To solve the above stated problems, “damascene” method has been applied effectively, whereby a pattern of interconnection grooves is first etched in the surface of a layer of oxide dielectric; and the surfaces of grooves are coated first with a thin barrier and seed layers and then filled with copper. The unwanted copper metal on the substrate surface is then removed from the surface by a CMP (chemical-mechanical polish) process. However, as the width of interconnections becomes thinner, these grooves would have a higher aspect ratio. There is great difficulties to fill them using conventional means.
It is known that metal films can be deposited using a variety of processes such as CVD (chemical vapor deposition), PVD (physical vapor deposition), electroplating, and electroless plating. Of these techniques, electroplating and electroless plating are the most economical and promising. At present, electroplating is the more mature technology and is being applied in development and production of 0.18-0.13 μm copper lines in IC circuits, using exclusively the damascene method for Cu delineation. However, it is apparent that the electroplating technique has its limitations in further scaling down the geometry of the device. To pre-condition an electroplating step, a thin but continuous metallic seed layer must first be deposited on the substrate by another method for the purpose of current conduction. Utilization of a limited number of discrete contacts with the seed layer at the perimeter of the wafer usually produces higher current densities at the contact points than at other portion of the wafer; non-uniformity of voltage drop on the wafer surface in turn causes non-uniformity in the deposits of plated material's thickness. Although this non-uniformity can be compensated by the provision of additional electrically conductive elements at the wafer periphery, it adds to the complexity of equipment, and increases costs of production.
As the geometries of circuits are scaled down further, the sizes of features such as vias and trenches also are reduced. As a result, it becomes more difficult to provide continuous barrier and seed layers. In addition, the thickness ratio of the seed layers in the trenches will become disproportionally larger as compared to the copper layer thickness in the trenches; keeping this ratio constant will aggravate the non-uniformity of the electro-plated film.
Electroless plating is a deposition process for metals on a catalytic surface from an electrolyte solution without an external source of current. Electroless deposition has always been processed in a batch mode because its deposition rate is usually very low. It has always been deposited in a big tank with multiple work pieces in order for the process to be economically viable.
Since single wafer and clustered systems for IC processing have become the common and prevailing trend in the IC industry, big open tanks with processing chemicals as required by the electroless plating process are not compatible or easily implemented in IC fabs, and are wasteful of the expensive ultra-clean fabrication space because of their large footprint.
Both the electro- and electroless plating techniques suffer from a common problem because their operations usually take place in open electrolyte baths. When wafers are transferred from the baths to be cleaned, foreign particles tend to be deposited on the surface of the substrate and oxidation of the catalytic surface in the exposure to air may result in poor catalytic activity and poor metal deposits. Another common problem is the possible occurrence of non-wetting of deep and narrow trenches or holes in the substrate surface because of liquid evaporation. It is more desirable not to transfer the wafer between the process steps and to avoid exposing the wafer to air by using a single processing bath; and to move the different fluids for each step in the process through the process chamber.
The above problem are being addressed by the system described in U.S. Pat. No. 5,830,805 issued in 1998 to Y. Shacham-Diamond, et. al. This patent discloses an electroless deposition apparatus and method, whereby electroless deposition on a wafer takes place in a closed process chamber. It is thus possible to subject the wafer to more than one processing fluids and processing steps while retaining it within the chamber. The invention is useful for manufacturing processes that include depositing, etching, cleaning, rinsing, and drying. The process chamber used in the preferred embodiments of the apparatus of the above patent is an enclosed container capable of holding one or more semiconductor wafers. In spite of their advantages, the embodiment for a single wafer chamber suffers from the shortcoming of low wafer throughput and would be unsuitable for the manufacturing environment. Their batch processing embodiment, on the other hand would have a issue of film thickness uniformity control within the wafer and from wafer to wafer.
U.S. Pat. No. 6,322,677 issued in 2001 to D. Woodruff, et al. discloses a lift and rotate assembly for use in a workpiece processing station and a method of attaching the same. The lift and rotate assembly includes a body having a slim profile and pins located on opposite sides for mounting the assembly onto a tool frame. The lift and rotating assembly further includes a rotating mechanism coupling a processing head to the body, and for rotating the process head with respect to the body. The rotating mechanism includes a motor, wherein the motor is located within the processing head and the shaft of the motor is coupled to and rotationally fixed with respect to the body. The lift and rotate assembly further includes a lift mechanism for lifting the process head with respect to the body. A cable assembly within the lift and rotate assembly includes a common cable loop for feeding additional length of cable along both the lift direction and the rotational direction of movement. The station contains a plurality of processing chambers arranged in two parallel rows with an object handling unit moveable on the tracks between the rows of the processing chambers. In order to load and unload the objects into and from the individual processing chambers, it is necessary to open the top cover of each chamber and to transfer the object using the transport mechanism with a complicated trajectory of an object-handling mechanism. Such an arrangement is purely linear and cannot rationally use the floor space of the clean room.
U.S. Pat. No. 6,267,853 issued in 2001 to Y. Dordi, et al. discloses an electro-chemical deposition system which generally comprises a mainframe having a mainframe wafer transfer robot, a loading station disposed in connection with the mainframe, one or more processing cells disposed in connection with the mainframe, and an electrolyte supply fluidly connected to the one or more electrical processing cells. Preferably, the electro-chemical deposition system includes an edge bead removal/spin-rinse-dry (EBR/SRD) station disposed on the mainframe adjacent the loading station, a rapid thermal anneal chamber attached to the loading station, a seed layer repair station disposed on the mainframe, and a system controller for controlling the electro-chemical deposition process and the components of the electro-chemical deposition system. In fact, this is a cluster tool station with various functional units arranged around a common object transfer mechanism for transferring objects between various functional units in accordance with a required sequence. A disadvantage of the aforementioned arrangement that the entire cluster machine can be placed into the clean room only as an indivisible or integral system which does not allow placement of those units which otherwise could be placed into a service area beyond the boundaries of the expensive clean-room floor space.
The same disadvantages as in Dordi's, et al. invention are inherent in the substrate plating apparatus disclosed in U.S. Pat. No. 6,294,059 issued in 2001 to A. Hongo, et al. The apparatus includes a plating unit for forming a plated layer on a surface of the substrate including the interconnection region, a chemical mechanical polishing unit for chemically mechanically polishing the substrate to remove the plated layer from the surface of the substrate leaving a portion of the plated layer in the interconnection region, a cleaning unit for cleaning the substrate after the plated layer is formed or the substrate is chemically mechanically polished, a drying unit for drying the substrate after the substrate is cleaned, and a substrate transfer unit for transferring the substrate to and from each of the first plating unit, the first chemical mechanical polishing unit, the cleaning unit, and the drying unit. The first plating unit, the first chemical mechanical polishing unit, the cleaning unit, the drying unit, and the substrate transfer unit are combined into a unitary arrangement. In other words, similar to the previous patents, the station of U.S. Pat. No. 6,294,059 can also be classified as a cluster-tool station with a common robot which serves different functional units combined into an indivisible unity.